1. Field of the Invention
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors (MOSFETs), and, more particularly, to MOSFETs that achieve improved carrier mobility through the incorporation of strained silicon.
2. Related Technology
MOSFETs are a common component of integrated circuits (ICs). FIG. 1 shows a conventional MOSFET device. The MOSFET is fabricated on a semiconductor substrate 10 within an active area bounded by shallow trench isolations 12 that electrically isolate the active area of the MOSFET from other IC components fabricated on the substrate 10.
The MOSFET is comprised of a gate electrode 14 that is separated from a channel region 16 in the substrate 10 by a thin first gate insulator 18 such as silicon oxide or oxide-nitride-oxide (ONO). To minimize the resistance of the gate 14, the gate 14 is typically formed of a doped semiconductor material such as polysilicon.
The source and drain of the MOSFET are provided as deep source and drain regions 20 formed on opposing sides of the gate 14 and channel region 16. Source and drain silicides 22 are formed on the source and drain regions 20 and are comprised of a compound comprising the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni) to reduce contact resistance to the source and drain regions 20. The source and drain regions 20 are formed deeply enough to extend beyond the depth to which the source and drain silicides 22 are formed. The source and drain regions 20 are implanted subsequent to the formation of a spacer 24 around the gate 14 and gate insulator 18 which serves as an implantation mask to define the lateral position of the source and drain regions 20 relative to the channel region 16 beneath the gate.
The gate 14 likewise has a silicide 26 formed on its upper surface. The gate structure comprising a polysilicon material and an overlying silicide is sometimes referred to as a polycide gate.
The source and drain of the MOSFET further comprise shallow source and drain extensions 28. As dimensions of the MOSFET are reduced, short channel effects resulting from the small distance between the source and drain cause degradation of MOSFET performance. The use of shallow source and drain extensions 28 rather than deep source and drain regions near the ends of the channel 16 helps to reduce short channel effects. The shallow source and drain extensions are implanted prior to the formation of the spacer 24 and after formation of a thin spacer 30, and the gate 14 and thin spacer 30 act as an implantation mask to define the lateral position of the shallow source and drain extensions 28 relative to the channel region 16. Diffusion during subsequent annealing causes the source and drain extensions 28 to extend slightly beneath the gate 14.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of silicon so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is generally more widely spaced than a pure silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET using a strained silicon layer is shown in FIG. 2. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 on which is formed an epitaxial layer of strained silicon 34. The MOSFET uses conventional MOSFET structures including deep source and drain regions 20, shallow source and drain extensions 28, a gate oxide layer 18, a gate 14 surrounded by a gate spacers 30, 24, silicide source and drain contacts 22, a silicide gate contact 26, and shallow trench isolations 12. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
One detrimental effect observed in MOSFETs having small critical dimensions is a short channel effect known as punchthrough. Punchthrough occurs when the channel length of the device is sufficiently short to allow the depletion regions at the ends of the source and drain extensions to overlap, thus effectively merging the two depletion regions. Any increase in reverse-bias drain voltage beyond that required to establish punchthrough lowers the potential energy barrier for majority carriers in the source, resulting in a punchthrough current between the source and drain that must be suppressed for proper device operation.
The punchthrough problem is exacerbated in PMOS devices because the typical p-type dopant boron (B) has a high rate of diffusion in silicon. As a result, shallow source and drain extensions tend to diffuse during activation, causing the ends of the source and drain extensions to become nearer to each other and to therefore create a greater risk of punchthrough. This problem occurs in both regular PMOS devices and PMOS devices employing a strained silicon layer as shown in FIG. 2.